1. Field of the Invention
The present invention relates to an information processing apparatus, a control method for the information processing apparatus, and a program.
2. Description of the Related Art
Recently, an information processing apparatus configured with a asymmetrical multiprocessor system which combines a central processing unit (CPU) (general-use processor) and a digital signal processor (DSP) (processor specialized in data processing) has been increased.
In the asymmetrical multiprocessor system, in many cases, the CPU and the DSP take a master-slave configuration. In the master-slave configuration, the CPU serves as a master processor and the DSP serves as a slave processor. The CPU and the DSP share a memory, and the CPU controls activation and operation of the DSP.
Conventionally, in the information processing apparatus configured with the master-slave asymmetrical multiprocessor system, processing as illustrated in FIG. 5 has been executed when the system is activated. First, the CPU executes activation processing of the CPU (time t1 to t3). Next, the CPU downloads software of the DSP (time t3 to t4). Next, the CPU releases reset of the DSP (time t4 to t5). Then, the DSP executes activation processing of the DSP (time t5 to t6).
As a technique for reducing electric power consumption of hardware, there is a technique referred to as a clock gating. The clock gating is a technique for stopping supply of clock to the hardware, when the hardware is not operating (See Japanese Patent Application Laid-Open No. 5-235710).
In general, when the hardware is reset, supplying the clock to the hardware is to be continued. Therefore, in the information processing apparatus of the above described configuration, electric power consumption cannot be reduced by applying the clock gating, if the DSP is not executing any processing while the CPU executes activation processing or the like.